Ram五, 08/11/2019 - 23:27 的修訂版本

修訂版本可以讓你追蹤文章的多個版本的不同之處。

 

 

 


Singe Rank Memory

 

外觀

It can be memory with chips on only one side of the stick of memory,(多數)

however Single Rank Memory can also have chips on both sides of the Stick as well.

Hardware

Channel -> DIMM(Dual In-line Memory Module) -> Rank -> Chip -> Row/Col

DIMM 頻寬: 64bit

記憶體顆粒寬: 8 bit => 1 Rank = 8 Chip (8x8 bit)

Label

Single Rank has a 1RxN on it, for example 1Rx4 or 1Rx8,

On the flip side Dual Rank Memory has a 2RxN on it, for example 2Rx4 or 2Rx8.

2R = 2 個 Rank

x8 =每個 Rank 有8顆IC

原理

每個 Rank 以相同的 Chip Select(CS# (CS0, CS1)) 連接在一起

也就是說當北橋發出 CS# 訊號時, 這個Rank內的所有IC顆粒便同時會被 Enable

(Only one rank is accessible at a time)

 


DDR

 

DDR 全稱為 Double Data Rate SDRAM

DDR SDRAM 在一個時鐘週期要傳輸兩次數據

Label" DDR3-1600

 => Clock: 800 MHz

 => Bandwith: 800 x 2 x 64 bit = 12800 MB/s

 


時延(Latency)

 

Column Access Strobe (CAS)  又稱 CL

顆粒的時延

Delay time between the READ command and the moment data is available

Format: CL-tRCD-tRP-tRAS

CL = Column Address Strobe (重要)

If a row has already been selected,

it tells us how many clock cycles we'll have to wait for a first result

tRCD = Row Address (RAS) to Column Address (CAS) Delay (重要)

Once we send the memory controller a row address,

we'll have to wait this many cycles before accessing one of the row's columns

讀資料情況

CL 後 loop tRCD 去讀取資料

tRP = Row Precharge Time

If we already have a row selected,

we'll have to wait this number of cycles before selecting a different row.

to access the data in a different row =  tRP + tRCD + tCL cycles

tRAS = Row Active Time

This is the minimum number of cycles that a row has to be active for to ensure

we'll have enough time to access the information that's in it.

tRAS = tCL + tRCD + tRP

i.e.

Kingston DDR-3 1600MHz 8GB KVR16N11/8

 


電壓

 

DDR3 分為 1.5V 與 1.35V (DDR3L) 兩個版本

 


Quad-rank